用CMOS工艺实现非接触IC卡天线的集成化设计

论述了用CMOS工艺实现非接触式IC卡天线的集成化需要考虑的各个方面,建立了集成天线的模型,给出了合理的设计方案,并通过实验验证了模型和设计方案.实验结果表明,采用片上天线完全可以提供非接触式IC卡工作所需要的能量.在频率为2 2 .5 MHz、感应强度为6×10 - 4 T的磁场中,面积为2 m m×2 mm的集成天线可以为10 kΩ的负载提供1.2 2 5 m W的能量.     

PC机系统的优化

根据MS－DOS存在的缺陷较全面地论述了PC机优化的概念，技术及方法．     

指令cache体系结构级功耗控制策略研究

 随着工艺尺寸缩小及处理器频率提高,功耗问题已成为当代微处理器设计面临的主要挑战.传统的指令cache(I-Cache)功耗控制策略一般只单独降低指令cache的动态或者静态功耗.提出的两种改进的功耗控制策略,基于昏睡指令cache体系结构,能够更有效地同时降低指令cache的动态和静态功耗.一种称作"使用双预测端口路预测器的多路路预测策略",另一种称作"基于分阶段访问cache的按需唤醒预测策略",分别用于处理器前端流水线级数保持不变和可以增加额外前端流水线级数两种情形.实验结果表明:与传统的策略相比,提出的两种策略具有更优的能量效率,可以在不显著影响处理器性能的前提下,更有效地降低指令cache和处理器的功耗.     

Controller synthesis with guaranteed closed-loop phase constraints

In this paper, we present an analysis and synthesis approach for guaranteeing that the phase of a single-input, single-output closed-loop transfer function is contained in the interval [−α,α] for a given α>0 at all frequencies. Specifically, we first derive a sufficient condition involving a frequency domain inequality for guaranteeing a given phase constraint. Next, we use the Kalman–Yakubovich–Popov theorem to derive an equivalent time domain condition. In the case where , we show that frequency and time domain sufficient conditions specialize to the positivity theorem. Furthermore, using linear matrix inequalities, we develop a controller synthesis approach for guaranteeing a phase constraint on the closed-loop transfer function. Finally, we extend this synthesis approach to address mixed gain and phase constraints on the closed-loop transfer function.     

An LMI approach to synthesis subject to almost asymptotic regulation constraints

A multi-objective controller synthesis problem is considered in which an output is to be regulated approximately by assuring a bound on the steady-state peak amplification in response to an infinite-energy disturbance, while also guaranteeing a desired level of performance measured in terms of the worst-case energy gain from a finite-energy input to a performance output. Relying on a characterization of the controllers with which almost asymptotic regulation is accomplished, the problem of guaranteeing the desired level of performance is reduced to solving a system of linear matrix inequalities subject to a set of linear equality constraints. Based on the solution of this system, a procedure is outlined for the construction of a suitable controller whose order is equal to the order of the plant plus the order of the exogenous system.     

On the design of on-chip instruction caches

Cache memories reduce memory latency and traffic in computing systems. Most existing caches are implemented as board-based systems. Advancing VLSI technology will soon permit significant caches to be integrated on chip with the processors they support. In designing on-chip caches, the constraints of VLSI become significant. The primary constraints are economic limitations on circuit area and off-chip communications. The paper explores the design of on-chip instruction-only caches in terms of these constraints. The primary contribution of this work is the development of a unified economic model of on-chip instruction-only cache design which integrates the points of view of the cache designer and of the floorplan architect. With suitable data, this model permits the rational allocation of constrained resources to the achievement of a desired cache performance. Specific conclusions are that random line replacement is superior to LRU replacement, due to an increased flexibility in VLSI floorplan design; that variable set associativity can be an effective tool in regulating a chip's floorplan; and that sectoring permits area efficient caches while avoiding high transfer widths. Results are reported on economic functionality, from chip area and transfer width to miss ratio. These results, or the underlying analysis, can be used by microprocessor architects to make intelligent decisions regarding appropriate cache organizations and resource allocations.     

NONH:A New Cache-Based Coherence Protocol for Linked List Structure DSM System and Its Performance Evaluation

The management of memory coherence is an important problem in distributed shared memory(DSM)system.In a cache-based coherence DSM system using linked list structure,the key to maintaining the coherence and improving system performance is how to manage the owner in the linked list.This paper presents the design of a new management protocol-NONH(New-Owner New-Head)and its performance evaluation.The analysis results show that this protocol can improve the scalability and performence of a coherent DSM system using linked list.It is also suitable for managing the cache coherency in tree-like hierarchical architecture.     

多机Cache中存储访问不命中率的理论分析

本文主要研究了多处理机系统中访问ｃａｃｈｅ不命中的平均情况。从多机间相互干扰的角度，分析了访问ｃａｃｈｅ的平均不命中次数，本文还从算法设计出发，提出了分析ｃａｃｈｅ伪共享的直观方法——访问模式图     

Dynamic Affinity Cluster Allocation in a Shared Disks Cluster

A shared disks (SD) cluster couples multiple computing nodes for high performance transaction processing, and all nodes share a common database at the disk level. In the SD cluster, a front-end router selects a node for an incoming transaction to be executed. An affinity-based routing can increase the buffer hit ratio of each node by clustering transactions referencing similar data to be executed on the same node. However, the affinity-based routing is non-adaptive to the changes of the system load. This means that a specific node would be overloaded if corresponding transactions rush into the system. In this paper, we propose a new transaction routing algorithm, named Dynamic Affinity Cluster Allocation (DACA). DACA can make an optimal balance between the affinity-based routing and indiscriminate sharing of load in the SD cluster. As a result, DACA can increase the buffer hit ratio and reduce the frequency of inter-node buffer invalidations while achieving the dynamic load balancing.     

An Effective Cache Replacement Algorithm in Transcoding-Enabled Proxies

In this paper, we address the problem of cache replacement for transcoding proxy caching. Transcoding proxy is a proxy that has the functionality of transcoding a multimedia object into an appropriate format or resolution for each client. We first propose an effective cache replacement algorithm for transcoding proxy. In general, when a new object is to be cached, cache replacement algorithms evict some of the cached objects with the least profit to accommodate the new object. Our algorithm takes into account of the inter-relationships among different versions of the same multimedia object, and selects the versions to replace according to their aggregate profit which usually differs from simple summation of their individual profits as assumed in the existing algorithms. It also considers cache consistency, which is not considered in the existing algorithms. We then present a complexity analysis to show the efficiency of our algorithm. Finally, we give extensive simulation results to compare the performance of our algorithm with some existing algorithms. The results show that our algorithm outperforms others in terms of various performance metrics.